//序列检测

// check the Seq is 110010
module top #(
	parameter CheckSeqLEN = 6 
	)(
	input clk,    
	input rst_n ,
	input Seq_in ,
	output Done   
);

	logic [CheckSeqLEN - 1 : 0 ]  checkseq = 6'b110010 ;

	logic [CheckSeqLEN - 1  : 0 ] state  ; 

	assign Done = state == 6  ;

	always_ff @ (posedge  clk or negedge rst_n) begin : stateMachine
		if(!rst_n)begin
			state <= 'd0 ;
			// DoneR <= 0;
		end else begin
			case(state)
				0 : begin state <= Seq_in == checkseq[CheckSeqLEN-1] ? 1 : 0 ;end 
				1 : begin state <= Seq_in == checkseq[CheckSeqLEN-2] ? 2 : 0 ;end 
				2 : begin state <= Seq_in == checkseq[CheckSeqLEN-3] ? 3 : 2 ;end 
				3 : begin state <= Seq_in == checkseq[CheckSeqLEN-4] ? 4 : 1 ;end 
				4 : begin state <= Seq_in == checkseq[CheckSeqLEN-5] ? 5 : 0 ;end 
				5 : begin state <= Seq_in == checkseq[CheckSeqLEN-6] ? 6 : 2 ;end 
				default : begin state <= 0 ;end 
			endcase
		end


	end



endmodule : top